Project 6: The JFET

Objective

The objective of this project is to determine the drain current that flows when a JFET is fully ON, and the gate voltage needed to fully shut the JFET OFF, using the circuit shown in Figure 4.22.

Figure 4.22.

General Instructions

After the circuit is set up, change the gate voltage (VGS) by adjusting the potentiometer. Measure the drain current (ID) for each VGS value. As you work through the project, observe how the drain current drops toward zero as you increase VGS. When the JFET is OFF, ID is at zero; when the JFET is fully ON, ID is at its maximum (called IDSS).

Parts List

• You need the following equipment and supplies:
• One 6-volt battery pack (4 AA batteries)
• One 12-volt battery pack (8 AA batteries)
• One multimeter set to mA
• One multimeter set to measure DC voltage
• One 10 k potentiometer
• One breadboard
• Two terminal blocks
• One 2N3819 JFET (Figure 4.23 shows the pinout for the 2N3819.)

Figure 4.23

Step-by-Step Instructions

Set up the circuit shown in Figure 4.22. If you have some experience in building circuits, this schematic (along with the previous parts list) should provide all the information you need to build the circuit. If you need a bit more help building the circuit, look at the photos of the completed circuit in the “Expected Results” section.

Carefully check your circuit against the diagram, especially the orientation of the JFET to ensure that the drain, gate, and source leads are connected correctly. One unusual aspect of this circuit you may want to check is that the +V bus of the 6-volt battery pack should be connected to the ground bus of the 12-volt battery pack.

1. After you check your circuit, follow these steps, and record your measurements in the blank table following the steps:
2. Adjust the potentiometer to set VGS at 0 volts. (Your multimeter may indicate a few tenths of a millivolt; that's close enough.)
3.  Measure and record VGS and ID.
4. Adjust the potentiometer slightly to give a higher value of VGS.
5. Measure and record the new values of VGS and ID.
6. Repeat steps 3 and 4 until ID drops to 0 mA.
7. VGS (Volts) ID (mA)
8. Graph the points recorded in the table, using the blank graph in Figure 4.24. Draw a curve through the points. Your curve should look like the one in Figure 4.22.

Figure 4.24

Expected Results

Figure 4.25 shows the breadboarded circuit for this project.

Figure 4.25

Figure 4.26 shows the test setup for this project.

Figure 4.26

 Compare your measurements with the ones shown in the following table. You should see a similar trend in the measured values, not exactly the same values.

Figure 4.27 is the V-I curve generated using the measurements shown in the preceding table. This graph is called the transfer curve for the JFET.

Figure 4.27

With the potentiometer set to 0 ohms (point A in Figure 4.22), the voltage from the gate to the source is zero (VGS = 0). The current that flows between the drain and source terminals of the JFET at this time is at its maximum value and is called the saturation current (IDSS).

Note: One property of the saturation current is that when VGS is set at zero, and the transistor is fully ON, the current doesn't drop as long as the value of VDS is above a few volts. If you have an adjustable power supply, you can determine the value of VDS at which ID starts to drop by starting with the power supply set at 12 volts. Watch the value of ID as you lower the power supply voltage until you see ID start to decrease.